This invention relates to rate limited common mode control for pulse-width modulation drives.
Many motor control applications make use of pulse-width modulated (PWM) voltages to drive a motor at various speeds. In some examples, motor control applications use a PWM controller in conjunction with a PWM inverter (e.g., a three phase inverter). The controller and inverter can be used to control both the voltage level and the frequency of the signals that are used to drive the motor.
A common method for generating pulse-width modulated voltages with a three-phase inverter bridge is to calculate duty-cycles Da, Db, and Dc that are proportional to a set of commanded voltages Va, Vb and Vc. The duty-cycles are then sent to a circuit that controls the switches of the inverter.
Factors such as frequency and current magnitude directly affect power losses in PWM inverters. For example, a transition on a high current phase can dissipate substantial energy in the switching device (e.g., a transistor) during a transition between off and on states.
Switching losses can be reduced by reducing switching frequency or by reducing currents to be conducted. However, such reduction methods may not be sufficient in some applications. Thus, other methods for reducing switching losses are desirable.
In some examples, multiple phase control voltages are used to control motor speed, torque, or position in a feedback loop. Noise in the phase control voltages can cause the PWM controller to introduce unwanted, rapid switching of a common mode voltage as a consequence of some PWM algorithms. This unwanted switching can translate into unwanted switching of the PWM signals that are used to drive the motor. The power losses introduced by such unwanted switching can be significant. Thus, system designers may strive to reduce unwanted switching.